The subject matter relates to semiconductor design technology, and more particularly, to a semiconductor memory device including a word line driving device for reduced power consumption.
While a memory capacity of a semiconductor integrated circuit, and more particularly, a semiconductor memory device such as a dynamic random access memory (DRAM) has increased, an external input source voltage has progressively reduced. The semiconductor memory device demands for a high speed operation and for maintaining a time according to a cell data maintenance at least same. In order to correspond to these demands, a boosted voltage generating circuit is included in the semiconductor memory device. The boosted voltage generating circuit boosts an external source voltage to an increased voltage for driving the semiconductor memory device thereby realizing high-speed operation of an internal memory cell.
In case of a general double data rate 2 (DDR2) device, a boosted voltage generating circuit supplies a high voltage of 3.5V by boosting an external source voltage of 1.8V. That is, the boosted voltage generating circuit approximately doubles the external source voltage of 1.8V. In general, the semiconductor memory devices use a Tripler for supplying a boosted voltage. However, this presents challenges for designing a semiconductor memory device fit for low power applications.
Because current consumption increases in accordance with progressively increasing memory capacity, it is necessary to find ways to decrease current consumption. Towards this, multiple boosted voltage generating circuits are included in a semiconductor memory device, with boosted voltage generating circuits respectively designed for particular demanded voltages of the device. Desirable characteristics for a boosted voltage generating circuit design include low current consumption, a small chip area footprint, and the ability to generate a various boosted voltages with only minor design changes.
In a conventional semiconductor memory device, the boosted voltage generating circuit supplies a high voltage VPP to a word line of a memory array and a peripheral circuit. The high voltage VPP generated by the boosted voltage generating circuit is supplied to a substrate voltage generating circuit so that other demanded voltages are derived from the high voltage VPP.
Further, the high voltage VPP is used as a power source of a word line activating circuit. For example, in a DDR2 device where the high voltage VPP is used to activate 4,096 cell transistors, there is large current consumption. In order to design a low power semiconductor memory, it is desirable that minimize use of the high voltage VPP.
FIG. 1 is a block diagram of a conventional word line control unit of a semiconductor memory device.
As shown, the conventional word line control unit includes a first driving signal generating unit 140, a second driving generating signal unit 150, a voltage supplying unit 160 and a word line control unit 170. The first driving signal generating unit 140 generates a first word line driving signal MWLB based on plural address information signals BAX34, BAX56 and BAX78 and a word line activation signal WLOFFB. The second driving signal generating unit 150 generates a second word line driving signal FXB based on the word line activation signal WLOFFB and plural address information signals BAX01 and BAX02. The voltage supplying unit 160 outputs a driving source signal FX at a voltage level of a high voltage VPP (Hereinafter, referring to as “a high voltage level”) having a boosted level higher than that of an external voltage VDD based on the second word line driving signal FXB. The word line control unit 170 drives a word line WL with a voltage level of the driving source signal FX in response to the first word line driving signal MWLB and the second word line driving signal FXB.
The semiconductor memory device decodes commands and addresses input from external and internal commands to activate the word line WL during an active operation according to read/write commands and a refresh operation, but deactivate the word line WL during a precharge operation. When the semiconductor memory device requires to deactivate the word line WL, a word line off signal WLOFF (not shown, corresponding to an inverted signal of the word line activation signal WLOFFB) for deactivating the word line WL is activated to a logic high level. Also, the word line activation signal WLOFFB inputted to the first and second driving signal generating units 140 and 150 becomes a logic low level. When the semiconductor memory device performs an active operation, the word line off signal WLOFF becomes a logic low level and the word line activation signal WLOFFB is activated to a logic high level. Generally, the word line off signal WLOFF or the word line activation signal WLOFFB is generated in response to a precharge command PCG for indicating the precharge operation.
To activate the word line WL at the high voltage level, the first and second driving signal generating units 140 and 150 outputs the first and second word line driving signals MWLB and FXB with a logic low level. The voltage supplying unit 160 supplies the driving source signal FX of the high voltage level to the word line control unit 170 in response to the second word line driving signal FXB. Thereafter, to deactivate the word line WL, the first and second driving signal generating units 140 and 150 outputs the first and second word line driving signals MWLB and FXB with a logic high level. Thus, the word line control unit 170 discharges the high voltage level supplied to the word line WL to thereby deactivating the word line WL.
FIG. 2 is a circuit diagram of the voltage supplying unit 160 shown in FIG. 1.
As shown, the voltage supplying unit 160 outputs the driving source signal FX with the high voltage level or a voltage level of a ground voltage VSS (Hereinafter, referring to as “a ground voltage level”) in response to the second word line driving signal FXB.
In detail, the voltage supplying unit 160 includes a PMOS transistor for outputting the driving source signal FX with the high voltage level when the second word line driving signal FXB has a logic low level, and an NMOS transistor for outputting the driving source signal FX with the ground voltage level when the second word line driving signal FXB has a logic high level.
FIG. 3 is a circuit diagram of the word line control unit 170 shown in FIG. 1.
As shown, the word line control unit 170 includes a PMOS transistor PM1, a first NMOS transistor NM1, and a second NMOS transistor NM2. The PMOS transistor PM1 drives the word line WL to the voltage level of the driving source signal FX in response to an activation of the first word line driving signal MWLB. The first NMOS transistor NM1 makes the word line WL to the ground voltage level in response to an inactivation of the first word line driving control signal MWLB. The second NMOS transistor NM2 makes the word line WL to the ground voltage level in response to an activation of the second word line driving signal FXB.
Upon operation, if the first word line driving signal MWLB is activated to a logic low level, the PMOS transistor PM1 becomes active and drives the word line WL to the voltage level of the driving source signal FX. If both of the first word line driving signal MWLB and the second word line driving signal FXB are inactivated at a logic high level, the first and second NMOS transistors NM1 and NM2 having a gate receiving the first word line driving signal MWLB and the second word line driving signal FXB become active and drive the word line WL to the ground voltage level.
The aforesaid word line control unit 170 may supply the high voltage level to the word line WL in response to the address information signals BAX01, BAX02, BAX34, BAX56 and BAX78. Herein, the address information signals are generated by decoding addresses (BA0 to BA8) inputted through address pins, and the semiconductor memory device includes the word line control unit according to predetermined groups of the addresses for designating unit cells.
Hereinafter, an operation of the word line control unit 170 shown in FIG. 1 will be described briefly.
First of all, after finishing the precharge operation, an address, along with an active command ACT for access of a memory, is supplied. The plurality of address information signals BAX01, BAX02, BAX34, BAX56 and BAX78 are activated to a logic high level by decoding the address. At this time, the word line activation signal WLOFFB is activated to a logic high level.
At the same time, first driving signal generating unit 140 activates the first word line driving signal MWLB at a logic low level according as the plural address information signals BAX34, BAX56 and BAX78 are activated to a logic high level. The second driving signal generating unit 150 activates the second word line driving signal FXB to a logic low level according as the address information signals BAX01 and BAX02 are activated to a logic high level. The voltage supplying unit 160 outputs the driving source signal FX to the high voltage level in response to an activation of the second word line driving signal FXB. Accordingly, the word line control unit 170 drives the word line WL to the voltage level of the driving source signal FX of the high voltage level in response to an activation of the first word line driving signal MWLB.
If a precharge command PCG is applied, the word line activation signal WLOFFB is inactivated to a logic low level.
The first driving signal generating unit 140 deactivates the first word line driving signal MWLB to a logic high level in response to a deactivation of the word line activation signal WLOFFB. The second driving signal generating unit 150 deactivates the second word line driving signal FXB to a logic high level in response to the activation of the word line activation signal WLOFFB. The voltage supplying unit 160 outputs the driving source signal FX of the ground voltage level in response to the second word line driving signal FXB of a logic high level. The word line control unit 170 drives the word line WL to the ground voltage level in response to the first word line driving signal MWLB of a logic high level.
As described above, when the address is input with the active command ACT, the semiconductor memory device including a conventional word line control unit drives the corresponding word line WL to the high voltage level. Further, if the precharge command PCG is input, the semiconductor memory device deactivates the corresponding activated word line WL.
However, when the word line WL is activated from the ground voltage level to the high voltage level, causing a voltage level of the word line WL to raise suddenly, large current consumption occurs. In particular, the number of unit cells coupled to the word line WL increases according as the memory capacity increases, and thus large current consumption can occur. It makes difficult to design the semiconductor memory device fit for low power circumstance.